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? semiconductor ML9211 1/19 general description the ML9211 is a full cmos controller/driver for duplex or triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. it consists of a 56-segment driver multiplexed to drive up to 168 segments, and 10-bit digital dimming circuit. ML9211 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the vfd driver with keyscan and a/d converter function. ML9211 provides an interface with a microcontroller only by three signal lines: data in, clock and cs. features ? logic supply voltage (v dd ) : 4.5 to 5.5v ? driver supply voltage (v disp ) : 8 to 18v ? duplex/triplex (1/2 duty / 1/3 duty) selectable dup/ tri =1/2 duty selectable at "h" level dup/ tri =1/3 duty selectable at "l" level ? number of display segments max. 112-segment display (during 1/2 duty mode) max. 168-segment display (during 1/3 duty mode) ? master/slave selectable m/ s =master mode selectable at "h" level m/ s =slave mode selectable at "l" level ? interface with a microcontroller three lines: cs, clock, and data in ? 56-segment driver outputs : i oh =C5ma at v oh =v disp C0.8v (seg1 to 37) (can be directly connected to vfd tube : i oh =C10ma at v oh =v disp C0.8v (seg38 to 56) and require no external resistors) : i ol =500 m a at v ol =2v (seg1 to 56) ? 3-grid pre-driver outputs : i oh =C5.0ma at v oh =v disp C0.8v (require external drivers) i ol =10ma at v ol =2v ? logic outputs : i oh =C200 m a at v oh =v dd C0.8v i ol =200 m a at v ol =0.8v ? built-in digital dimming circuit (10-bit resolution) ? built-in oscillation circuit (external r and c) ? built-in power-on-reset circuit ? package options: 80-pin plastic qfp (qfp80-p-1420-0.80-bk) product name: ML9211ga 80-pin plastic qfp (qfp80-p-1414-0.65-k) product name: ML9211gp preliminary ? semiconductor ML9211 56-bit duplex/triplex (1/2 duty / 1/3 duty) vf controller/driver with digital dimming e2c0045-19-83 this version: aug. 1999
? semiconductor ML9211 2/19 block diagram timing generator dim out sync out1 sync out2 dim in sync in1 sync in2 m/ s dup/ tri osc control out1-56 56bit shift register in1-10 dimming latch out1-10 10bit digital dimming por osc0 cs clock data in out1-3 3bit shift register por por por 4h out1-56 segment latch 3 in1-56 0h 3h por out1-56 segment latch 2 in1-56 0h 2h por out1-56 segment latch 1 in1-56 0h 1h por mode select in1-3 por 0h 4h power on reset v dd l-gnd por out1-56 168 to 56 segment control in1-56 in1-56 in1-56 56 segment driver v disp d-gnd 3 grid pre driver grid2 grid3 grid1 seg56 seg1
? semiconductor ML9211 3/19 input and output configuration schematic diagram of driver output circuit v disp output d-gnd d-gnd v disp
? semiconductor ML9211 4/19 pin configuration (top view) nc: no connection 80-pin plastic qfp (qfp80-p-1420-0.80-bk) nc 41 seg1 42 seg2 43 seg3 44 seg4 45 seg5 46 seg6 47 seg7 48 seg8 49 seg9 50 seg10 51 seg11 52 seg12 53 seg13 54 seg14 55 seg15 56 seg16 57 seg17 58 seg18 59 seg19 60 seg20 61 seg21 62 seg22 63 seg23 64 d-gnd 40 dim out 39 sync out 1 38 sync out 2 37 m/ s 36 dup/ tri 35 osc0 34 l-gnd 33 nc 32 data in 31 clock 30 cs 29 sync in 2 28 sync in 1 27 dim in 26 v dd 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 d-gnd nc grid3 grid2 grid1 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 v disp seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 v disp
? semiconductor ML9211 5/19 nc: no connection 80-pin plastic qfp (qfp80-p-1414-0.65-k) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 seg39 seg38 v disp seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 v disp seg23 seg22 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc d-gnd v dd dim in sync in 1 sync in 2 cs clock data in nc l-gnd osc0 dup/ tri m/ s sync out 2 sync out 1 dim out d-gnd nc seg1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 grid1 grid2 grid3
? semiconductor ML9211 6/19 pin descriptions symbol qfp-1 * type description v disp 65, 80 power supply pins for vfd driver circuit. these should be connected externally. v dd 25 power supply pin for logic drive. d-gnd 24, 40 l-gnd 33 seg1 to 37 42 to 64, 66 to 79 o d-gnd is ground pin for the vfd driver circuit. l-gnd is ground pin for the logic circuit. these should be connected externally. segment (anode) signal output pins for a vfd tube. these pins can be directly connected to the vfd tube. external circuit is not required. i oh C5 ma seg38 to 56 1 to 19 o segment (anode) signal output pins for a vfd tube.these pins can be directly connected to the vfd tube. external circuit is not required. i oh C10 ma grid2 21 o inverted grid signal output pins. for pre-driver, the external circuit is required. i ol 10 ma cs 29 i chip select input pin. data is not transferred when cs is set to a low level. clock 30 i shift clock input pin. serial data shifts at the rising edge of the clock. data in 31 i serial data input pin (positive logic). data is input to the shift register at the rising edge of the clock signal. dup/ tri 35 i duplex/triplex operation select input pin. duplex (1/2 duty) operation is selected when this pin is set to v dd . triplex (1/3 duty) operation is selected when this pin is set to l-gnd. m/ s 36 i master/slave mode select input pin. master mode is selected when this pin is set to v dd . slave mode is selected when this pin is set to l-gnd. dimming pulse input. when the slave mode is selected, connect this pin to the master side dim out pin at the slave mode. the pulse width of the all segment output are controlled by a input pulse width of dim in. when the master mode is selected, the input level of this pin is ignored. connect this pin to v dd or l-gnd at the master mode. the pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. dim in 26 i sync in 2 28 i synchronous signal input. when the slave mode is selected, connect these pins to the master side sync out 1 and 2 pins. when the master mode is selected, the input level of these pins are ignored. connect these pins to v dd or l-gnd at the master mode. dim out 39 o dimming pulse output. connect this pin to the slave side dim in pin. qfp-2 * 63 78 23 22, 38 31 40 to 62, 64 to 77 79, 80, 1 to 17 19 27 28 29 33 34 24 26 37 20 18 22 20 grid1 grid3 sync in 1 27 25 pin
? semiconductor ML9211 7/19 symbol qfp-1 * type description sync out 1 38 synchronous signal output. connect these pins to the slave side sync in 1 and 2 pins. osc0 34 i/o rc oscillator connecting pins. oscillation frequency depends on display tubes to be used. for details, refer to electrical characteristics. qfp-2 * 36 32 sync out 2 37 o 35 pin v dd osc0 r c absolute maximum rating recommended operating conditions parameter symbol v disp driver supply voltage v dd logic supply voltage v ih high level input voltage v il low level input voltage f c clock frequency t op operating temperature condition min. typ. max. unit 8.0 13.0 18.0 v 4.5 5.0 5.5 v all inputs except osc0 0.8v dd v all inputs except osc0 0.2v dd v 2.0 mhz C40 +85 c f osc oscillation frequency r=10k w 5%, c=27pf5% 2.6 3.3 4.0 mhz f fr frame frequency r=10k w 5%, c=27pf5% 211 269 325 hz 1/3 duty 1/2 duty 317 403 488 hz parameter symbol condition ratings unit v disp C0.3 to +20 v driver supply voltage v dd v logic supply voltage v in v input voltage p d qfp80-p-1420-0.80-bk mw power dissipation t stg c storage temperature i o1 seg1 to 37 ma i o2 seg38 to 56 ma output current i o3 grid1 to 3 ma i o4 dim out, sync out1, sync out2 ma C0.3 to +6.5 C0.3 to v dd +0.3 760 C55 to +150 C10.0 to +2.0 C20.0 to +2.0 C10.0 to +20.0 C2.0 to +2.0 qfp80-p-1414-0.65-k 630 ta 3 25c * qfp-1: qfp80-p-1420-0.80-bk qfp-2: qfp80-p-1414-0.65-k
? semiconductor ML9211 8/19 electrical characteristics dc characteristics parameter symbol v ih high level input voltage v il low level input voltage i ih high level input current i il low level input current v oh1 v oh2 v oh3 high level output voltage condition min. max. unit 0.8v dd v 0.2v dd v v ih =v dd C1.0 +1.0 m a v il =gnd C1.0 +1.0 m a v disp C0.8 v v disp C0.8 v v disp C0.8 v v dd C0.8 v v disp =9.5v applied pin *1) *1) *1) *1) seg1-37 seg38-56 grid1-3 v oh4 *2) v dd =4.5v i oh1 =C5ma i oh2 =C10ma i oh3 =C5ma i oh4 =C200 m a v ol1 v ol2 v ol3 low level output voltage 2.0 v 2.0 v 2.0 v 0.8 v v disp =9.5v seg1-37 seg38-56 grid1-3 v ol4 *2) v dd =4.5v i ol1 =500 m a i ol2 =500 m a i ol3 =10ma i ol4 =200 m a 5.0 ma i dd v dd supply current 100 m a i disp v disp r=10k w 5%, c=27pf5%, no load ta=C40 to +85c,v disp =8.0 to 18.0v, v dd =4.5 to 5.5v *1) cs, clock, data in, dim in, sync in 1, sync in 2, m/ s , dup/ tri *2) dim out, sync out 1, sync out 2
? semiconductor ML9211 9/19 ac characteristics timing diagram l data input timing C0.8v dd C0.2v dd C0.8v dd C0.2v dd C0.8v dd C0.2v dd cs clock data in t ds t dh t css 1/f c t cw t cw t csh t csl valid valid valid valid l reset timing t pof t prz v dd cs t rsoff C0.8v dd C0.0v C0.8v dd C0.0v l driver output timing C0.8v disp C0.2v disp seg1-56, grid1-3 t r t r t f parameter symbol f c clock frequency t cw clock pulse width t ds data setup time t dh data hold time t csl cs off time t css t r t prz cs setup time (cs-clock) output slew rate time v dd rise time condition min. max. unit 2.0 mhz 200 ns 200 ns 200 ns 20 m s 200 ns t r =20% to 80% 2.0 m s t f =80% to 20% 2.0 m s mounted in a unit 100 m s c l =100pf t csh cs hold time (clock-cs) 200 ns t pof v dd off time mounted in a unit, v dd =0.0v 5.0 ms t rsoff cs wait time 400 m s t f ta=C40 to +85c,v disp =8.0 to 18.0v, v dd =4.5 to 5.5v
? semiconductor ML9211 10/19 l output timing (duplex operation) *1bit time=4/f osc (the dimming data is 1016/1024 in the master mode) grid1 v disp d-gnd grid2 v disp d-gnd grid3 seg1-56 v disp d-gnd dim out v dd l-gnd sync out1 v dd l-gnd sync out2 v dd l-gnd v disp d-gnd 2048bit times (1 display cycle) 1016bit times 1016bit times 1016bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1029bit times 1019bit times 1019bit times 1019bit times 1029bit times 1029bit times 5bit times 5bit times 5bit times 3bit times 8bit times 8bit times 8bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times l output timing (triplex operation) *1bit time=4/f osc (the dimming data is 1016/1024 in the master mode) grid1 v disp d-gnd grid2 v disp d-gnd grid3 seg1-56 v disp d-gnd dim out v dd l-gnd sync out1 v dd l-gnd sync out2 v dd l-gnd v disp d-gnd 3072bit times (1 display cycle) 1016bit times 1016bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1019bit times 1029bit times 1019bit times 1019bit times 1019bit times 1029bit times 5bit times 5bit times 5bit times 3bit times 8bit times 8bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 5bit times 1019bit times 1016bit times 8bit times
? semiconductor ML9211 11/19 l output timing (duplex operation) *1bit time=4/f osc (the dimming data is 64/1024 in the master mode) l output timing (triplex operation) *1bit time=4/f osc (the dimming data is 64/1024 in the master mode) grid1 v disp d-gnd grid2 v disp d-gnd grid3 seg1-56 v disp d-gnd dim out v dd l-gnd sync out1 v dd l-gnd sync out2 v dd l-gnd v disp d-gnd 2048bit times (1 display cycle) 64bit times 64bit times 64bit times 67bit times 67bit times 67bit times 67bit times 1981bit times 957bit times 3bit times 960bit times 67bit times 67bit times 1981bit times 1981bit times 67bit times 67bit times 67bit times 960bit times 960bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times grid1 v disp d-gnd grid2 v disp d-gnd grid3 seg1-56 v disp d-gnd dim out v dd l-gnd sync out1 v dd l-gnd sync out2 v dd l-gnd v disp d-gnd 3072bit times (1 display cycle) 64bit times 64bit times 67bit times 67bit times 67bit times 67bit times 1981bit times 957bit times 3bit times 960bit times 67bit times 67bit times 1981bit times 67bit times 67bit times 67bit times 960bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 957bit times 67bit times 64bit times 960bit times
? semiconductor ML9211 12/19 segment data input [function mode: 0 to 3] ? ML9211 receives the segment data when function mode 0 to 3 are selected. ? the same segment data is transferred to the 3 segment data latches corresponding to grid 1 to 3 at the same time when the function mode 0 is selected. ? the segment data is transferred to only one segment data latch corresponding to the specified grid when the function mode is 1, 2 or 3 is selected. ? segment output (seg1 to 56) becomes high level (lighting) when the segment data (s1 to s56) is set to "1". [data format] input data : 59 bits segment data : 56 bits mode data : 3 bits functional description power-on reset when power is turned on, the ML9211 is initialized by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: ? the contents of the shift registers and latches are set to "0". ? the digital dimming duty cycle is set to "0". ? all segment outputs are set to low level. ? all grid outputs are set to high level. data transfer method data can be transferred between the rising edge and the next falling edge of chip select input. the mode data, segment data and dimming data are written by a serial transfer method. the serial data is input to the shift register at the rising edge of a shift clock pulse. the mode data (m0 to m2) must be transferred after the segment data and dimming data succeedingly. when the chip select input falls, an internal load signal is automatically generated and data is loaded to the latches. function mode function mode is selected by the mode data (m0 to m2). the relation between function mode and mode data is as follows: function mode operating mode function data m0 m1 m2 000 0 segment data for grid1-3 input 100 1 segment data for grid1 input 010 2 segment data for grid2 input 110 3 segment data for grid3 input 001 4 digital dimming data input 1 s1 2 s2 3 s3 4 s4 53 s53 54 s54 55 s55 56 s56 57 m0 58 m1 59 m2 bit input data segment data (56bits) mode data ( 3bits )
? semiconductor ML9211 13/19 [bit correspondence between segment output and segment data] 1 s1 21 s21 2 s2 22 s22 3 s3 23 s23 4 s4 24 s24 5 s5 25 s25 6 s6 26 s26 7 s7 27 s27 8 s8 28 s28 9 s9 29 s29 10 s10 30 s30 11 s11 31 s31 12 s12 32 s32 13 s13 33 s33 14 s14 34 s34 15 s15 35 s35 16 s16 36 s36 seg n segment data seg n segment data 17 s17 37 s37 18 s18 38 s38 19 s19 39 s39 20 s20 40 s40 41 s41 42 s42 43 s43 44 s44 45 s45 46 s46 47 s47 48 s48 49 s49 50 s50 51 s51 52 s52 53 s53 54 s54 55 s55 56 s56 seg n segment data digital dimming data input [function mode: 4] ? ML9211 receives the digital dimming data when function mode 4 is selected. ? the output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. ? the 10-bit digital dimming data is input from lsb. [data format] input data : 13 bits digital dimming data: 10 bits mode data : 3 bits 1 d1 2 d2 3 d3 4 d4 7 d7 8 d8 9 d9 10 d10 11 m0 12 m1 13 m2 bit input data digital dimming data (10bits) mode data (3bits) 5 d5 6 d6 d10 0 0 1 1 1 1 d9 0 0 1 1 1 1 d8 0 0 1 1 1 1 d7 0 0 1 1 1 1 d6 0 0 1 1 1 1 d5 0 0 1 1 1 1 d4 0 0 0 1 1 1 d3 0 0 1 0 0 1 d2 0 0 1 0 0 1 d1 0 1 1 0 1 1 dimming data (msb) (lsb) duty cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024 lsb msb master mode master mode is selected when m/ s pin is set at high level. the master mode operation is as follows: ? the input levels of dim in, sync in1 and sync in2 are ignored, and these pins should be connected to l-gnd or v dd . ? brightness is adjusted by the internal digital dimming circuit. ? the segment latch1 to 3 corresponding to grid1 to 3 are selected by the internal timing generator.
? semiconductor ML9211 14/19 sync in 1 sync in 2 segment latch grid 0 0 no no 1 0 latch1 grid1 0 1 latch2 grid2 1 1 latch3 grid3 dim in seg1 to 56 0 low 1 high slave mode slave mode is selected when m/ s pin is set at low level. the slave mode operation is as follows: ? the internal dimming circuit is ignored. ? the pulse width of seg1 to 56 are controlled by the pulse width of dim in signal. ? the segment latch1 to 3 corresponding to grid1 to 3 are selected by sync in1 and sync in2 signals. ? the output levels of grid1 to 3 are set at high level. the output levels of dim out, sync out1 and sync out2 are set at low level. [correspondence between sync in1, 2 and segment latch1 to 3] [correspondence between dim in and seg1 to 56] note: low: lights off high: lights on
? semiconductor ML9211 15/19 application circuits 1. circuit for the duplex vfd tube with 128 segments (2 grid 112 anode) ML9211 (master) v disp v dd d-gnd l-gnd osc 0 clock data in cs dim in sync in 1 sync in 2 m/ s dup/ tri dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg56 ML9211 (slave) v disp v dd d-gnd l-gnd osc 0 clock data in cs dim in sync in 1 sync in 2 dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg56 v dd duplex vfd tube s110 s111 s112 s1 s2 s3 g1 g2 microcontroller v disp v dd m/ s gnd dup/ tri v dd ef gnd gnd gnd r c v dd gnd r c v dd
? semiconductor ML9211 16/19 2. circuit for the triplex vfd tube with 192 segments (3 grid 112 anode) ML9211 (master) v disp v dd d-gnd l-gnd osc 0 clock data in cs dim in sync in 1 sync in 2 dup/ tri m/ s dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg56 ML9211 (slave) v disp v dd d-gnd l-gnd clock data in cs dim in sync in 1 sync in 2 dup/ tri m/ s dim out sync out 1 sync out 2 grid2 grid1 grid3 seg1 seg56 v dd triplex vfd tube s110 s111 s112 s1 s2 s3 g1 g2 microcontroller v disp v dd gnd ef gnd gnd gnd r c v dd osc 0 gnd r c v dd g3
? semiconductor ML9211 17/19 notes on turning power on/off ? connect l-gnd and d-gnd externally to be an equal potential voltage. ? to avoid wrong operations, turn on the driver power supply after turning on the logic power supply. conversely, turn off the logic power supply after tuning off the driver power supply. [voltage] [ time ] v dd v disp
? semiconductor ML9211 18/19 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish
? semiconductor ML9211 19/19 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.85 typ. qfp80-p-1414-0.65-k mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-62

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